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FEATURES Rail-to-Rail Input and Output Swing Low Power: 60 A/Amplifier Gain Bandwidth Product: 450 kHz Single-Supply Operation: +3 V to +12 V Low Offset Voltage: 300 V max High Open-Loop Gain: 500 V/mV Unity-Gain Stable No Phase Reversal APPLICATIONS Battery Monitoring Sensor Conditioners Portable Power Supply Control Portable Instrumentation
Micropower, Rail-to-Rail Input and Output Operational Amplifiers OP196/OP296/OP496
PIN CONFIGURATIONS 8-Lead Narrow-Body SO
NULL 1 -IN A 2 +IN A 3 V- 4 8 NC
8-Lead Plastic DIP
OP196
7 V+ 6 OUT A 5 NULL
NULL 1 -IN A 2
OP196
8 NC 7 V+ 6 OUT A 5 NULL
+IN A 3 V- 4 NC = NO CONNECT
NC = NO CONNECT
8-Lead Narrow-Body SO
OUT A 1 -IN A 2 +IN A 3 8 V+
8-Lead Plastic DIP
OP296
7 OUT B 6 -IN B 5 +IN B
OUT A 1 -IN A 2 +IN A 3 V- 4
OP296
8
V+
7 OUT B 6 -IN B 5 +IN B
GENERAL DESCRIPTION
V- 4
The OP196 family of CBCMOS operational amplifiers features micropower operation and rail-to-rail input and output ranges. The extremely low power requirements and guaranteed operation from +3 V to +12 V make these amplifiers perfectly suited to monitor battery usage and to control battery charging. Their dynamic performance, including 26 nV/Hz voltage noise density, recommends them for battery-powered audio applications. Capacitive loads to 200 pF are handled without oscillation. The OP196/OP296/OP496 are specified over the HOT extended industrial (-40C to +125C) temperature range. +3 V operation is specified over the 0C to +125C temperature range. The single OP196 and the dual OP296 are available in 8-lead plastic DIP and SO-8 surface mount packages. The quad OP496 is available in 14-lead plastic DIP and narrow SO-14 surface mount packages.
14-Lead Narrow-Body SO
OUT A 1 -IN A 2 +IN A 3 +V 4 +IN B 5 -IN B 6 OUT B 7 14 OUT D 13 -IN D 12 +IN D
8-Lead TSSOP
1 OUT A -IN A +IN A V- 4 8 V+ OUT B -IN B +IN B 5
OP296
14-Lead Plastic DIP
OUT A 1 -IN A 2
14 OUT D 13 -IN D 12 +IN D
OP496
11 V- 10 +IN C 9 -IN C 8 OUT C
+IN A 3 +V 4 +IN B 5 -IN B 6
OP496
11
V-
10 +IN C 9 8 -IN C OUT C
OUT B 7
14-Lead TSSOP (RU Suffix)
1 OUT A -IN A +IN A V+ +IN B -IN B OUT B 14 OUT D -IN D +IN D V- +IN C -IN C OUT C 8
OP496
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
OP196/OP296/OP496-SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V
S CM
= +2.5 V, TA = +25 C unless otherwise noted)
Min Typ 35 Max 300 650 800 1.2 50 8 20
+5.0
Parameter INPUT CHARACTERISTICS Offset Voltage
Symbol VOS
Conditions OP196G, OP296G, OP496G -40C TA +125C OP296H, OP496H -40C TA +125C -40C TA +125C -40C TA +125C 0 V VCM 5.0 V, -40C TA +125C RL = 100 k, 0.30 V VOUT 4.7 V, -40C TA +125C G Grade, Note 1 H Grade, Note 1 G Grade, Note 2 H Grade, Note 2 IL = -100 A IL = 1 mA IL = 2 mA IL = -1 mA IL = -1 mA IL = -2 mA
Units V V V mV nA nA nA
V
Input Bias Current Input Offset Current
Input Voltage Range
IB IOS
VCM
10 1.5
0
Common-Mode Rejection Ratio Large Signal Voltage Gain
CMRR AVO VOS VOS/T
65
dB
150
200 550 1 1.5 2
Long-Term Offset Voltage Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing High
V/mV V mV V/C V/C V V V mV mV mV mA
VOH VOL IOUT PSRR ISY
4.85 4.30
Output Voltage Swing Low
Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
4.92 4.56 4.1 36 350 750 4
70 550
2.5 V VS 6 V, -40C TA +125C VOUT = 2.5 V, R L = -40C TA +125C RL = 100 k
85 45 0.3 350 47 0.8 26 0.19 60 80
dB A A V/s kHz Degrees V p-p nV/Hz pA/Hz
SR GBP om en p-p en in
0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
NOTES 1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 C, with an LTPD of 1.3. 2 Offset voltage drift is the average of the -40C to +25C delta and the +25C to +125C delta. Specifications subject to change without notice.
-2-
REV. B
OP196/OP296/OP496 ELECTRICAL SPECIFICATIONS
Parameter INPUT CHARACTERISTICS Offset Voltage VOS
(@ V S = +3.0 V, VCM = +1.5 V, TA = +25 C unless otherwise noted)
Conditions OP196G, OP296G, OP496G 0C TA +125C OP296H, OP496H 0C TA +125C Min Typ 35 Max 300 650 800 1.2 50 8
+3.0
Symbol
Units V V V mV nA nA
V
Input Bias Current Input Offset Current
Input Voltage Range
IB IOS
VCM
10 1
0
Common-Mode Rejection Ratio Large Signal Voltage Gain Long-Term Offset Voltage Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low POWER SUPPLY Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
CMRR AVO VOS VOS/T
0 V VCM 3.0 V, 0C TA +125C RL = 100 k G Grade, Note 1 H Grade, Note 1 G Grade, Note 2 H Grade, Note 2 IL = 100 A IL = -100 A VOUT = 1.5 V, R L = 0C TA +125C RL = 100 k
60 80
200 550 1 1.5 2
dB V/mV V mV V/C V/C V mV A A V/s kHz Degrees V p-p nV/Hz pA/Hz
VOH VOL ISY
2.85 70 40 60 80
SR GBP om en p-p en in
0.25 350 45 0.8 26 0.19
0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
NOTES 1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 C, with an LTPD of 1.3. 2 Offset voltage drift is the average of the 0C to +25C delta and the +25C to +125C delta. Specifications subject to change without notice.
REV. B
-3-
OP196/OP296/OP496 ELECTRICAL SPECIFICATIONS (@ V = +12.0 V, V
S
CM
= +6 V, TA = +25 C unless otherwise noted)
Min Typ 35 Max 300 650 800 1.2 50 8 15
+12
Parameter INPUT CHARACTERISTICS Offset Voltage
Symbol VOS
Conditions OP196G, OP296G, OP496G 0C TA +125C OP296H, OP496H 0C TA +125C -40C TA +125C -40C TA +125C 0 V VCM +12 V, -40C TA +125C RL = 100 k G Grade, Note 1 H Grade, Note 1 G Grade, Note 2 H Grade, Note 2 IL = 100 A IL = 1 mA IL = -1 mA IL = -1 mA VOUT = 6 V, RL = -40C TA +125C
Units V V V mV nA nA nA
V
Input Bias Current Input Offset Current
Input Voltage Range
IB IOS
VCM
10 1
0
Common-Mode Rejection Ratio Large Signal Voltage Gain Long-Term Offset Voltage Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Swing High Output Voltage Swing Low Output Current POWER SUPPLY Supply Current per Amplifier Supply Voltage Range DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
CMRR AVO VOS VOS/T
65 300
1000 550 1 1.5 2
dB V/mV V mV V/C V/C V V mV mV mA A A V V/s kHz Degrees V p-p nV/Hz pA/Hz
VOH VOL IOUT ISY VS SR GBP om en p-p en in
11.85 11.30 4 70 550
+3 RL = 100 k 0.3 450 50 0.8 26 0.19
60 80 +12
0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz
NOTES 1 Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125 C, with an LTPD of 1.3. 2 Offset voltage drift is the average of the -40C to +25C delta and the +25C to +125C delta. Specifications subject to change without notice.
-4-
REV. B
OP196/OP296/OP496
ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Temperature Range -40C to +125C -40C to +125C Package Description 8-Lead Plastic DIP 8-Lead SOIC 8-Lead Plastic DIP 8-Lead SOIC 8-Lead TSSOP Package Option N-8 SO-8 N-8 SO-8 RU-8
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . +15 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range P, S, RU Package . . . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature Range OP196G, OP296G, OP496G, H . . . . . . . - 40C to +125C Junction Temperature Range P, S, RU Package . . . . . . . . . . . . . . . . . . . - 65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300C Package Type 8-Lead Plastic DIP 8-Lead SOIC 8-Lead TSSOP 14-Lead Plastic DIP 14-Lead SOIC 14-Lead TSSOP
3 JA JC
Model OP196GP OP196GS
OP296GP -40C to +125C OP296GS -40C to +125C OP296HRU -40C to +125C OP496GP -40C to +125C OP496GS -40C to +125C OP496HRU -40C to +125C
Units C/W C/W C/W C/W C/W C/W
14-Lead Plastic DIP N-14 14-Lead SOIC SO-14 14-Lead TSSOP RU-14
103 158 240 83 120 180
43 43 43 39 36 35
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For supply voltages less than +15 V, the absolute maximum input voltage is equal to the supply voltage. 3 JA is specified for the worst case conditions, i.e., JA is specified for device in socket for P-DIP package; JA is specified for device soldered in circuit board for SOIC and TSSOP packages.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP196/OP296/OP496 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, pro per ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-5-
OP196/OP296/OP496-Typical Performance Characteristics
250 VS = 3V TA = 25 C COUNT = 400 25 VS = 5V VCM = 2.5V TA = -40 C TO 125 C
200 QUANTITY - Amplifiers
20 QUANTITY - Amplifiers
150
15
100
10
50
5
0 -250 -200 -150 -100 -50 0 50 100 150 INPUT OFFSET VOLTAGE - V
200
250
0 -4.0 -3.5
-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 INPUT OFFSET DRIFT, TCVOS -
0 0.5 V/ C
1.0
Figure 1. Input Offset Voltage Distribution
Figure 4. Input Offset Voltage Distribution (TCVOS )
250 VS = 5V TA = 25 C COUNT = 400
25 VS = 12V VCM = 6V TA = -40 C TO
200 QUANTITY - Amplifiers
20 QUANTITY - Amplifiers
125 C
150
15
100
10
50
5
0 -250 -200 -150 -100 -50 0 50 100 150 INPUT OFFSET VOLTAGE - V
200
250
0 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 INPUT OFFSET DRIFT, TCVOS - V/ C
1.0
1.5
Figure 2. Input Offset Voltage Distribution
Figure 5. Input Offset Voltage Distribution (TCVOS )
250 VS = 12V TA = 25 C COUNT = 400
600
3V INPUT OFFSET VOLTAGE - V 400 VCM = 200
200 QUANTITY - Amplifiers
VS VS 2
12V
150
100
0
50
-200
0 -250 -200 -150 -100 -50 0 50 100 150 INPUT OFFSET VOLTAGE - V
200
250
-400 -75
-50
-25
0
25 50 75 TEMPERATURE - C
100
125
150
Figure 3. Input Offset Voltage Distribution
Figure 6. Input Offset Voltage vs. Temperature
-6-
REV. B
OP196/OP296/OP496
25 VS = 5V VCM = 2.5V 20 INPUT BAIS CURRENT - nA OUTPUT VOLTAGE - mV 100 VS = 1.5V 1000
15
SOURCE SINK
10
10
5
0 -75
-50
-25
0
25 50 75 TEMPERATURE - C
100
125
150
1 0.001
0.01
0.1 1 LOAD CURRENT - mA
10
Figure 7. Input Bias Current vs. Temperature
Figure 10. Output Voltage to Supply Rail vs. Load Current
16
1000
INPUT BIAS CURRENT - nA
VS = 12 OUTPUT VOLTAGE - mV 100
2.5V
SOURCE SINK
8
10
4
2
3
5 SUPPLY VOLTAGE - Volts
12
14
1 0.001
0.01
0.1 1 LOAD CURRENT - mA
10
Figure 8. Input Bias Current vs. Supply Voltage
Figure 11. Output Voltage to Supply Rail vs. Load Current
40 30 INPUT BIAS CURRENT - nA 20 10 0 -10 -20 -30 -40 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 COMMON-MODE VOLTAGE - Volts VS = TA = 2.5V 25 C
1000
VS = OUTPUT VOLTAGE - mV 100
6V
SOURCE SINK
10
2.0
2.5
1 0.001
0.01
0.1 1 LOAD CURRENT - mA
10
Figure 9. Input Bias Current vs. Common-Mode Voltage
Figure 12. Output Voltage to Supply Rail vs. Load Current
REV. B
-7-
OP196/OP296/OP496-Typical Performance Characteristics
4.95 I L = 100 A 80 VOH OUTPUT VOLTAGE - Volts 4.70 OPEN-LOOP GAIN - dB I L = 1mA 4.45 70 60 GAIN 50 40 30 20 PHASE 10 0 3.7 -75 -50 -25 0 25 50 75 TEMPERATURE - C 100 125 150 -10 10 100 1k 10k FREQUENCY - Hz 100k 135 180 225 1M 0 45 90 PHASE SHIFT - C PHASE SHIFT - C 90 VS = 2.5V TA = -40 C
4.2 VS = 3.85 5V
I L = 2mA
Figure 13. Output Voltage Swing vs. Temperature
Figure 16. Open-Loop Gain and Phase vs. Frequency (No Load)
0.80 VS = VOL OUTPUT VOLTAGE - Volts 0.60 OPEN-LOOP GAIN - dB I L = -1mA 0.50 5V
90 80 70 60 GAIN 50 40 30 20 10 I L = -100 A 0 100 125 150 -10 10 100 1k 10k FREQUENCY - Hz 100k PHASE 135 180 225 1M 0 45 90 VS = TA = 2.5V 125 C
0.30
0.10
-75
-50
-25
0
25 50 75 TEMPERATURE - C
Figure 14. Output Voltage Swing vs. Temperature
Figure 17. Open-Loop Gain and Phase vs. Frequency (No Load)
90 80 70 OPEN-LOOP GAIN - dB OPEN-LOOP GAIN - V/mV 60 GAIN 50 40 30 20 PHASE 10 0 -10 10 100 1k 10k FREQUENCY - Hz 100k 135 180 225 1M 0 45 90 PHASE SHIFT - C VS = TA = 2.5V 25 C
950 VS = 800 5V 0.3V < VO < 4.7V RL = 100k
650
500
350
200 -75
-50
-25
0
25 50 75 TEMPERATURE - C
100
125
150
Figure 15. Open-Loop Gain and Phase vs. Frequency (No Load)
Figure 18. Open-Loop Gain vs. Temperature
-8-
REV. B
OP196/OP296/OP496
600 VS = TA = 5V 25 C 160 140 120 100 CMRR - dB 80 60 40 20 100 0 -20 0 150 100 50 10 LOAD - k 2 1 -40 100 1k 10k 100k FREQUENCY - Hz 1M 10M VS = 2.5V TA = 25 C ALL CHANNELS 500 OPEN-LOOP GAIN - V/mV
400
300
200
Figure 19. Open Loop Gain vs. Resistive Load
Figure 22. CMRR vs. Frequency
70 60 50 CLOSED-LOOP GAIN - dB 40 30 20 10 0 VS = 2.5V RL = 10k TA = 25 C
160 140 120 100 PSRR - dB 80 60 40 -PSRR 20 0 -20 100 1k 10k FREQUENCY - Hz 100k 1M -40 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M +PSRR VS = TA = 5V 25 C
-10 -20 -30 10
Figure 20. Closed-Loop Gain vs. Frequency
Figure 23. PSRR vs. Frequency
1000 900 800 OUTPUT IMPEDANCE - 700 600 ACL = 10 500 400 300 200 100 0 100 1k 10k FREQUENCY - Hz 100k 1M ACL = 1 VS = TA = 2.5V 25 C MAXIMUM OUTPUT SWING - Volts
6 VS = 2.5V VIN = 5V p-p AV = 1 RL = 100k
5
4
3
2
1
0 1k
10k
100k FREQUENCY - Hz
1M
Figure 21. Output Impedance vs. Frequency
Figure 24. Maximum Output Swing vs. Frequency
REV. B
-9-
OP196/OP296/OP496-Typical Performance Characteristics
90 80 70 VS = 60 50 40 30 20 -75 -50 VS = 3V VS = 5V 12V CURRENT NOISE DENSITY - pA/ Hz 0.6 VS = 2.5V TA = 25 C VCM = 0V 0.5
ISY/AMPLIFIER - A
0.4
0.3
0.2
0.1
-40 -25
0 25 50 85 75 TEMPERATURE - C
100 125 150
0 1
10
100 FREQUENCY - Hz
1k
Figure 25. Supply Current/Amplifier vs. Temperature
Figure 28. Input Bias Current Noise Density vs. Frequency
55 TA = 25 C
10 8 6 VS = TA = 6V 25 C OUTPUT SWING
50 4 ISY/AMPLIFIER - A INPUT STEP - Volts 2 0 -2 -4 -6 -8 35 1 3 5 7 9 11 SUPPLY VOLTAGE - Volts 12 13 -10 0
TO 0.1%
45
40
- OUTPUT SWING
5
10 15 20 SETTLING TIME - s
25
30
Figure 26. Supply Current/Amplifier vs. Supply Voltage
Figure 29. Settling Time to 0.1% vs. Step Size
80 70 60 50 40 30
10 100 90
VOLTAGE NOISE DENSITY - nV/ Hz
VS = 2.5V TA = 25 C VCM = 0V
2mV
1s
20 10 0
0%
VS = 2.5V AV = 10k en = 0.8 V p-p
1
10
100 FREQUENCY - Hz
1k
Figure 27. Voltage Noise Density vs. Frequency
Figure 30. 0.1 Hz to 10 Hz Noise
-10-
REV. B
OP196/OP296/OP496
100mV
100 90 100 90
VS = 2.5V RL = 10k
10
0V
0%
20mV
VS = 2.5V AV = 1 RL = 10k CL = 100pF TA = 25 C
10 0%
2s
1V
10 s
Figure 31. Small Signal Transient Response
Figure 33. Large Signal Transient Response
100mV
100 90
100 90
VS = 2.5V RL = 100k
10
0V
0%
20mV
VS = 2.5V AV = 1 RL = 100k CL = 100pF TA = 25 C
10 0%
2s
1V
10 s
Figure 32. Small Signal Transient Response
CH A: 40.0 V FS MKR: 36.8 V/ Hz
Figure 34. Large Signal Transient Response
5.00 V/DIV
0Hz MKR: 1.00Hz BW: 145mHz
10Hz
Figure 35. 1/f Noise Corner, VS = 5 V, AV = 1,000
VCC R1 I1 R2 D3 Q11 Q5 2x Q3 1x 1x Q7 +IN Q1 Q2 2x 2x Q4 1x 1x Q13 Q8 2x Q9 Q10 QC2 R5 -IN R3A I2 R3B VEE 1* 5* R4B R4A I3 Q15 CC1 Q16 Q20 D7 1.5x D10 1x R9 Q14 D5 Q18 D6 2x Q19 1x Q23 QC1 CF1 CF2 CC2 OUT Q6 Q12 D4 Q17 D8 Q21 QL1 R6 R7 I4 R8 D9 I5 Q22
*OP196 ONLY
Figure 36. Simplified Schematic
REV. B
-11-
OP196/OP296/OP496
APPLICATIONS INFORMATION Functional Description
VOLTAGE - 5V/DIV
The OP196 family of operational amplifiers is comprised of singlesupply, micropower, rail-to-rail input and output amplifiers. Input offset voltage (VOS) is only 300 V maximum, while the output will deliver 5 mA to a load. Supply current is only 50 A, while bandwidth is over 450 kHz and slew rate is 0.3 V/s. Figure 36 is a simplified schematic of the OP196--it displays the novel circuit design techniques used to achieve this performance.
Input Overvoltage Protection
input current must be limited if the inputs are driven beyond the supply rails. In the circuit of Figure 38, the source amplitude is 15 V, while the supply voltage is only 5 V. In this case, a 2 k source resistor limits the input current to 5 mA.
5V
100 90
VS = 5V AV = 1 VIN 0
The OPx96 family of op amps uses a composite PNP/NPN input stage. Transistor Q1 in Figure 36 has a collector-base voltage of 0 V if +IN = VEE. If +IN then exceeds VEE, the junction will be forward biased and large diode currents will flow, which may damage the device. The same situation applies to +IN on the base of transistor Q5 being driven above VCC . Therefore, the inverting and noninverting inputs must not be driven above or below either supply rail unless the input current is limited. Figure 37 shows the input characteristics for the OPx96 family. This photograph was generated with the power supply pins connected to ground and a curve tracer's collector output drive connected to the input. As shown in the figure, when the input voltage exceeds either supply by more than 0.6 V, internal pnjunctions energize and permit current flow from the inputs to the supplies. If the current is not limited, the amplifier may be damaged. To prevent damage, the input current should be limited to no more than 5 mA.
8 6 INPUT CURRENT - mA
100
VOUT
10 0%
0
5V
TIME - 1ns/DIV
1ms
Figure 38. Output Voltage Phase Reversal Behavior
Input Offset Voltage Nulling
The OP196 provides two offset adjust terminals that can be used to null the amplifier's internal VOS. In general, operational amplifier terminals should never be used to adjust system offset voltages. A 100 k potentiometer, connected as shown in Figure 39, is recommended to null the OP196's offset voltage. Offset nulling does not adversely affect TCVOS performance, providing that the trimming potentiometer temperature coefficient does not exceed 100 ppm/C.
V+
2
90
7
4 2 0 -2 -4 -6 -8
OP196
4 3 1 100k 5
6
10 0%
V-
Figure 39. Offset Nulling Circuit
-1.5 -1 -0.5 0 0.5 1 1.5 INPUT VOLTAGE - Volts
Driving Capacitive Loads
Figure 37. Input Overvoltage I-V Characteristics of the OPx96 Family
Output Phase Reversal
OP196 family amplifiers are unconditionally stable with capacitive loads less than 170 pF. When driving large capacitive loads in unity-gain configurations, an in-the-loop compensation technique is recommended, as illustrated in Figure 40.
RG VIN CF RF
Some other operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. With these common-mode limited devices, external clamping diodes are required to prevent input signal excursions from exceeding the device's negative supply rail (i.e., GND) and triggering output phase reversal. The OPx96 family of op amps is free from output phase reversal effects due to its novel input structure. Figure 38 illustrates the performance of the OPx96 op amps when the input is driven beyond the supply rails. As previously mentioned, amplifier
RX
OP296
CL
VOUT
RX =
RO RG RF
WHERE RO = OPEN-LOOP OUTPUT RESISTANCE + ( |AICL| ) ( RFR RG ) CL RO
F
CF =
I+
Figure 40. In-the-Loop Compensation Technique for Driving Capacitive Loads
-12-
REV. B
OP196/OP296/OP496
A Micropower False-Ground Generator
Some single supply circuits work best when inputs are biased above ground, typically at 1/2 of the supply voltage. In these cases, a false-ground can be created by using a voltage divider buffered by an amplifier. One such circuit is shown in Figure 41. This circuit will generate a false-ground reference at 1/2 of the supply voltage, while drawing only about 55 A from a 5 V supply. The circuit includes compensation to allow for a 1 F bypass capacitor at the false-ground output. The benefit of a large capacitor is that not only does the false-ground present a very low dc resistance to the load, but its ac impedance is low as well.
+5V OR +12V 10k 240k 0.022 F
same potential. The result is that both terminals of R1 are at the same potential and no current flows in R1. Since there is no current flow in R1, the same condition must exist in R2; thus, the output of the circuit tracks the input signal. When the input signal is below 0 V, the output voltage of A1 is forced to 0 V. This condition now forces A2 to operate as an inverting voltage follower because the noninverting terminal of A2 is also at 0 V. The output voltage of VOUTA is then a full-wave rectified version of the input signal. A resistor in series with A1's noninverting input protects the ESD diodes when the input signal goes below ground.
Square Wave Oscillator
2
7
100 6 1F +2.5V OR +6V
OP196
3 240k 1F 4
Figure 41. A Micropower False-Ground Generator
Single-Supply Half-Wave and Full-Wave Rectifiers
An OP296, configured as a voltage follower operating from a single supply, can be used as a simple half-wave rectifier in low frequency (<400 Hz) applications. A full-wave rectifier can be configured with a pair of OP296s as illustrated in Figure 42.
R1 100k +5V +2Vp-p 2k
3 8 6
The oscillator circuit in Figure 43 demonstrates how a rail-torail output swing can reduce the effects of power supply variations on the oscillator's frequency. This feature is especially valuable in battery powered applications, where voltage regulation may not be available. The output frequency remains stable as the supply voltage changes because the RC charging current, which is derived from the rail-to-rail output, is proportional to the supply voltage. Since the Schmitt trigger threshold level is also proportional to supply voltage, the frequency remains relatively independent of supply voltage. For a supply voltage change from 9 V to 5 V, the output frequency only changes about 4 Hz. The slew rate of the amplifier limits the oscillation frequency to a maximum of about 200 Hz at a supply voltage of +5 V.
V+ 100k 59k
R2 100k 100k
3 2
8 1 4 R FREQ OUT fOSC = 1 < 200Hz @ V+ = +5V RC
<500Hz
A2
1 5
7
A1
2 4
1/2 OP296
1/2 OP296
VOUTA FULL-WAVE RECTIFIED OUTPUT VOUTB HALF-WAVE RECTIFIED OUTPUT
1/2 OP296/ OP496
C
Figure 43. Square Wave Oscillator Has Stable Frequency Regardless of Supply Voltage Changes
A 3 V Low Dropout, Linear Voltage Regulator
1V
INPUT VOUTB (HALF-WAVE OUTPUT)
100 90
500mV
500s
f = 500Hz
10
VOUTA (FULL-WAVE OUTPUT)
0%
500mV
Figure 44 shows a simple +3 V voltage regulator design. The regulator can deliver 50 mA load current while allowing a 0.2 V dropout voltage. The OP296's rail-to-rail output swing easily drives the MJE350 pass transistor without requiring special drive circuitry. With no load, its output can swing to less than the pass transistor's base-emitter voltage, turning the device nearly off. At full load, and at low emitter-collector voltages, the transistor beta tends to decrease. The additional base current is easily handled by the OP296 output. The AD589 provides a 1.235 V reference voltage for the regulator. The OP296, operating with a noninverting gain of 2.43, drives the base of the MJE350 to produce an output voltage of 3.0 V. Since the MJE350 operates in an inverting (commonemitter) mode, the output feedback is applied to the OP296's noninverting input.
Figure 42. Single-Supply Half-Wave and Full-Wave Rectifiers Using an OP296
The circuit works as follows: When the input signal is above 0 V, the output of amplifier A1 follows the input signal. Since the noninverting input of amplifier A2 is connected to A1's output, op amp loop control forces A2's inverting input to the
REV. B
-13-
OP196/OP296/OP496
MJE 350 VIN 5V TO 3.2V 8 1 3 30.9k 1% 2 44.2k 1% IL < 50mA VO 100 F
1/2 OP296
4
The next two DACs, B and C, sum their outputs into the other OP296 amplifier. In this circuit DAC C provides the coarse output voltage setting and DAC B is used for fine adjustment. The insertion of R1 in series with DAC B attenuates its contribution to the voltage sum node at the DAC C output.
A High-Side Current Monitor
1000pF 43k 1.235V
AD589
Figure 44. 3 V Low Dropout Voltage Regulator
Figure 45 shows the regulator's recovery characteristics when its output underwent a 20 mA to 50 mA step current change.
2V
STEP 50mA CURRENT CONTROL WAVEFORM 30mA
100 90
In the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistor's long-term reliability over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of prime importance in these designs. The circuit illustrated in Figure 47 is an example of a +5 V, single-supply high-side current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. This design uses an OP296's rail-to-rail input voltage range to sense the voltage drop across a 0.1 current shunt. A p-channel MOSFET is used as the feedback element in the circuit to convert the op amp's differential input voltage into a current. This current is then applied to R2 to generate a voltage that is a linear representation of the load current. The transfer equation for the current monitor is given by: R Monitor Output = R2 x SENSE x I L R1 For the element values shown, the Monitor Output's transfer characteristic is 2.5 V/A.
RSENSE 0.1 +5V +5V R1 100
3 8 1
OUTPUT
10 0%
10mV
50s
Figure 45. Output Step Load Current Recovery
Buffering a DAC Output
Multichannel TrimDACs(R) such as the AD8801/AD8803, are widely used for digital nulling and similar applications. These DACs have rail-to-rail output swings, with a nominal output resistance of 5 k. If a lower output impedance is required, an OP296 amplifier can be added. Two examples are shown in Figure 45. One amplifier of an OP296 is used as a simple buffer to reduce the output resistance of DAC A. The OP296 provides rail-to-rail output drive while operating down to a 3 V supply and requiring only 50 A of supply current.
+5V
IL +5V
1/2 OP296
2 4
S M1 3N163 MONITOR OUTPUT D R2 2.49k G
VREFH VDD VH VL VH VL VH VL R1 100k
OP296
SIMPLE BUFFER 0V TO +5V +4.983V +1.1mV
Figure 47. A High-Side Load Current Monitor
A Single-Supply RTD Amplifier
AD8801/ AD8803
VREFL GND DIGITAL INTERFACING OMITTED FOR CLARITY
SUMMER CIRCUIT WITH FINE TRIM ADJUSTMENT
Figure 46. Buffering a TrimDAC Output
The circuit in Figure 48 uses three op amps on the OP496 to produce a bridge driver for an RTD amplifier while operating from a single +5 V supply. The circuit takes advantage of the OP496's wide output swing to generate a bridge excitation voltage of 3.9 V. An AD589 provides a 1.235 V reference for the bridge current. Op amp A1 drives the bridge to maintain 1.235 V across the parallel combination of the 6.19 k and 2.55 M resistors, which generates a 200 A current source. This current divides evenly and flows through both halves of the bridge. Thus, 100 A flows through the RTD to generate an output voltage which is proportional to its resistance. For improved accuracy, a 3-wire RTD is recommended to balance the line resistance in both 100 legs of the bridge.
TrimDAC is a registered trademark of Analog Devices Inc.
-14-
REV. B
OP196/OP296/OP496
200 10-TURNS 26.7k 100 RTD 2.55M 100 26.7k GAIN = 259 +5V
1/4 OP496 A2
392 20k 100k 392
1/4 OP496 A3
VOUT
6.17k
1/4 OP496 A1
100k
Amplifiers A2 and A3 are configured in a two op amp instrumentation amplifier configuration. For ease of measurement, the IA resistors are chosen to produce a gain of 259, so that each 1C increase in temperature results in a 10 mV increase in the output voltage. To reduce measurement noise, the bandwidth of the amplifier is limited. A 0.1 F capacitor, connected in parallel with the 100 k resistor on amplifier A3, creates a pole at 16 Hz.
0.1 F NOTE: ALL RESISTORS 1% OR BETTER
AD589
37.4k +5V
Figure 48. A Single Supply RTD Amplifier
* OP496 SPICE Macro-model REV. B, 5/95 * ARG / ADSC * * Copyright 1995 by Analog Devices * * Refer to "README.DOC" file for License Statement. * Use of this model indicates your acceptance of the * terms and provisions in the License Statement. * * Node assignments * Noninverting input * Inverting input * Positive supply * Negative supply * Output * * .SUBCKT OP496 1 2 99 50 49 * * INPUT STAGE * IREF 21 50 1U QB1 21 21 99 99 QP 1 QB2 22 21 99 99 QP 1 QB3 4 21 99 99 QP 1.5 QB4 22 22 50 50 QN 2 QB5 11 22 50 50 QN 3 Q1 5 4 7 50 QN 2 Q2 6 4 8 50 QN 2 Q3 4 4 7 50 QN 1 Q4 4 4 8 50 QN 1 Q5 50 1 7 99 QP 2 Q6 50 3 8 99 QP 2 EOS 3 2 POLY(1) (17,98) 35U 1 Q7 99 1 9 50 QN 2 Q8 99 3 10 50 QN 2 Q9 12 11 9 99 QP 2 Q10 13 11 10 99 QP 2 Q11 11 11 9 99 QP 1 Q12 11 11 10 99 QP 1 R1 99 5 50K R2 99 6 50K R3 12 50 50K R4 13 50 50K IOS 1 2 0.75N C10 5 6 3.183P C11 12 13 3.183P REV. B
CIN 1 2 1P * * GAIN STAGE * EREF 98 0 POLY(2) (99,0) (50,0) 0 G1 98 15 POLY(2) (6,5) (13,12) 0 R10 15 98 251.641MEG CC 15 49 8P D1 15 99 DX D2 50 15 DX * * COMMON MODE STAGE * ECM 16 98 POLY(2) (1,98) (2,98) 0 R11 16 17 1MEG R12 17 98 10 * * OUTPUT STAGE * ISY 99 50 20U EIN 35 50 POLY(1) (15,98) 1.42735 Q24 37 35 36 50 QN 1 QD4 37 37 38 99 QP 1 Q27 40 37 38 99 QP 1 R5 36 39 150K R6 99 38 45K Q26 39 42 50 50 QN 3 QD5 40 40 39 50 QN 1 Q28 41 40 44 50 QN 1 QL1 37 41 99 99 QP 1 R7 99 41 10.7K I4 99 43 2U QD7 42 42 50 50 QN 2 QD6 43 43 42 50 QN 2 Q29 47 43 44 50 QN 1 Q30 44 45 50 50 QN 1.5 QD10 45 46 50 50 QN 1 R9 45 46 175 Q31 46 47 48 99 QP 1 QD8 47 47 48 99 QP 1 QD9 48 48 51 99 QP 5 R8 99 51 2.9K I5 99 46 1U Q32 49 48 99 99 QP 10 Q33 49 44 50 50 QN 4 .MODEL DX D() .MODEL QN NPN(BF=120VAF=100) .MODEL QP PNP(BF=80 VAF=60) .ENDS -15-
0.5 0.5 10U 10U
0.5 0.5
1
OP196/OP296/OP496
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 1 5 4
14-Lead Plastic DIP (N-14)
C2051b-0-2/98 PRINTED IN U.S.A.
8 0 0.028 (0.70) 0.020 (0.50) 0.795 (20.19) 0.725 (18.42)
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62)
14 1
8 7
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
PIN 1 0.210 (5.33) MAX
0.060 (1.52) 0.015 (0.38)
PIN 1 0.195 (4.95) 0.115 (2.93) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356)
0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC SEATING PLANE
0.160 (4.06) 0.115 (2.93)
0.130 (3.30) MIN SEATING 0.022 (0.558) 0.070 (1.77) PLANE 0.100 0.014 (0.356) (2.54) 0.045 (1.15) BSC
0.015 (0.381) 0.008 (0.204)
0.015 (0.381) 0.008 (0.204)
8-Lead Narrow Body SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 1 5 4
14-Lead Narrow-Body SOIC (SO-14)
0.3444 (8.75) 0.3367 (8.55)
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.1574 (4.00) 0.1497 (3.80) 0.0196 (0.50) x 45 0.0099 (0.25)
14 1
8 7
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
SEATING PLANE
0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC
0.0098 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
8-Lead TSSOP (RU-8)
0.122 (3.10) 0.114 (2.90)
14-Lead TSSOP (RU-14)
0.201 (5.10) 0.193 (4.90)
8
5
0.177 (4.50) 0.169 (4.30)
0.256 (6.50) 0.246 (6.25)
14
8
0.177 (4.50) 0.169 (4.30)
1
4
1
PIN 1 0.0256 (0.65) 0.006 (0.15) BSC 0.002 (0.05) PIN 1 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.006 (0.15) 0.002 (0.05)
7
SEATING PLANE
0.0118 (0.30) 0.0075 (0.19)
8 0
0.028 (0.70) 0.020 (0.50)
SEATING PLANE
0.0256 (0.65) BSC
0.0118 (0.30) 0.0075 (0.19)
-16-
0.256 (6.50) 0.246 (6.25) 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090)
REV. B

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